1. Field of the Invention
This invention relates to a semiconductor member and a process for preparing a semiconductor member, more particularly to a semiconductor which is suitable for separation of dielectric materials or electronic devices, integrated circuits prepared on a monocrystalline semiconductor layer on an insulating material.
2. Related Background Art
Formation of a monocrystalline Si semiconductor layer on an insulating material has been widely known as the silicon on insulator (SOI) technology, and since a large number of advantages which can not be reached by bulk Si substrates for preparation of conventional Si integrated circuits are possessed by the device utilizing the SOI structure, so many researches have been done. More specifically, by utilizing the SOI structure, the following advantages can be obtained:
1. Dielectric isolation can be easily done to enable high degree of integration; PA1 2. Radiation hardness is excellent; PA1 3. Stray capacity is reduced to attain high speed; PA1 4. Well formation step can be omitted; PA1 5. Latch-up can be prevented; PA1 6. Fully depleted field-effect transistor can be made by thin film formation. PA1 (1) After surface oxidation of a Si monocrystalline substrate, a window is formed to have the Si substrate partially exposed, and epitaxial growth is proceeded in the lateral direction with that exposed portion as the seed to form an Si monocrystalline layer on SiO.sub.2. (In this case, deposition of Si layer on SiO.sub.2 is accompanied). PA1 (2) By use of a Si monocrystalline substrate itself as active layer, SiO.sub.2 is formed therebeneath. (This method is accompanied with no deposition of Si layer). PA1 (3) After epitaxial growth of Si on a Si monocrystalline substrate, isolation separation is effected. (This method is accompanied with deposition of Si layer). PA1 1. An oxide film is formed on an Si monocrystalline substrate with V-grooves as anisotropically etched on the surface, a polycrystalline Si layer is deposited on the oxide film thick to the extent as the Si substrate, and thereafter by polishing from the back surface of the Si substrate, Si monocrystalline regions dielectrically separated by surrounding with the V-grooves on the thick polycrystalline Si layer are formed. In this method, although crystallinity is good, there are problems with respect to controllability and productivity in the step of depositing the polycrystalline Si thick as some hundred microns and the step in which the monocrystalline Si substrate is polished from the back surface to leave only the Si active layer as separated. PA1 2. This is the method called SIMOX (Separation by ion-implanted oxygen) in which an SiO.sub.2 layer is formed by ion implantation of oxygen into an Si monocrystalline substrate, which is one of the most mature methods because of good matching with the Si-IC (Integrated Circuit) process. However, for formation of the SiO.sub.2 layer, 10.sup.18 ions/cm.sup.2 or more of oxygen ions are required to be implanted, and the implantation time is very long to be not high in productivity, and also the wafer cost is high. Further, many crystal defects resin, and from an industrial point of view, no sufficient level of quality capable of preparing a device driven by minority carriers has been attained. PA1 3. This is the method to form an SOI structure by dielectric isolation according to oxidation of porous Si. This is a method in which an N-type Si layer is formed on the surface of a P-type Si monocrystalline substrate in shape of islands by way of proton ion implantation (Imai et al., J. Crystal Growth, Vol. 63; 547 (1983)), or by epitaxial growth and patterning; only the p-type Si substrate is made porous by anodization in HF solution so as to surround the Si islands from the surface; and then the N-type Si islands are dielectrically isolated by accelerated oxidation. In this method, the separated Si region is determined before the device steps, whereby there is the problem that the degree of freedom in device and circuit design may be limited in some cases. PA1 to provide a process for preparing a semiconductor member comprising the steps of: PA1 forming a member having a non-porous monocrystalline semiconductor region on a porous monocrystalline semiconductor region, PA1 bonding the surface of a member of which the surface is constituted of an insulating substance onto the surface of the non-porous monocrystalline semiconductor region, and then PA1 removing the porous monocrystalline semiconductor region by chemical etching; PA1 to provide a process for preparing a semiconductor member comprising the steps of: PA1 forming a member having a non-porous monocrystalline semiconductor region on a porous monocrystalline semiconductor region, PA1 forming a region constituted of an insulating substance on the non-porous monocrystalline semiconductor side of the member, then PA1 bonding the surface of a member of which the surface is constituted of an insulating substance onto the surface of the region constituted of the insulating substance, and PA1 removing the porous monocrystalline semiconductor region by chemical etching; PA1 to provide a process for preparing a semiconductor member comprising the steps of: PA1 making a non-porous monocrystalline semiconductor member porous to form a porous monocrystalline semiconductor region, PA1 forming a non-porous monocrystalline semiconductor region on the porous monocrystalline semiconductor region, PA1 bonding the surface of a member of which the surface is constituted of an insulating substance onto the surface of the non-porous monocrystalline semiconductor region, and PA1 removing the porous monocrystalline semiconductor region by chemical etching; PA1 to provide a process for preparing a semiconductor member comprising the steps of: PA1 making a non-porous monocrystalline semiconductor member porous to form a porous monocrystalline semiconductor region, PA1 forming a non-porous monocrystalline semiconductor region on the porous monocrystalline semiconductor region, PA1 forming a region constituted of an insulating substance on the non-porous monocrystalline semiconductor region side, PA1 bonding the surface of a member of which the surface is constituted of an insulating substance onto the surface of the region constituted of the insulating substance, and PA1 removing the porous monocrystalline semiconductor region by chemical etching; PA1 to provide a process for preparing a semiconductor member comprising the steps of: PA1 making a first non-porous monocrystalline semiconductor member partially porous to form a porous monocrystalline semiconductor region and a second non-porous monocrystalline semiconductor region, PA1 forming a third non-porous monocrystalline semiconductor region on the porous monocrystalline semiconductor region, PA1 bonding the surface of a member of which the surface is constituted of an insulating substance onto the surface of the third non-porous monocrystalline semiconductor region, and PA1 removing the second non-porous monocrystalline semiconductor region mechanically, and removing the porous monocrystalline semiconductor region by chemical etching; PA1 to provide a process for preparing a semiconductor member comprising the steps of: PA1 making a first non-porous monocrystalline semiconductor member partially porous to form a porous monocrystalline semiconductor region and a second non-porous monocrystalline semiconductor region, PA1 forming a third non-porous monocrystalline semiconductor region on the porous monocrystalline semiconductor region, PA1 forming a region constituted of an insulating substance on the third non-porous monocrystalline semiconductor region side, PA1 bonding the surface of a member of which the surface is constituted of an insulating substance onto the surface of the region constituted of the insulating substance, and PA1 removing the second non-porous monocrystalline semiconductor region mechanically, and removing the porous monocrystalline semiconductor region by chemical etching; PA1 to provide a process for preparing a semiconductor member comprising the steps of: PA1 forming a second monocrystalline semiconductor region of a second electroconduction type on a first monocrystalline semiconductor region of a first electroconduction type, PA1 making the first monocrystalline semiconductor region porous to form a porous monocrystalline semiconductor region, PA1 bonding the surface of a member of which the surface is formed of an insulating substance onto the surface of the second monocrystalline semiconductor region, and PA1 removing the porous monocrystalline semiconductor region by chemical etching; PA1 to provide a process for preparing a semiconductor member comprising the steps of: PA1 forming a second monocrystalline semiconductor region of a second electroconduction type on a first monocrystalline semiconductor region of a first electroconduction type, PA1 making the first monocrystalline semiconductor region porous to form a porous monocrystalline semiconductor region, PA1 forming a region constituted of an insulating substance on the second monocrystalline semiconductor region side, PA1 bonding the surface of a member of which the surface is formed of an insulating substance onto the surface of the second monocrystalline semiconductor region, and PA1 removing the porous monocrystalline semiconductor region by chemical etching; PA1 to provide a semiconductor member comprising: PA1 a first member having a non-porous monocrystalline semiconductor region on a porous monocrystalline semiconductor region, and PA1 a second member having the surface constituted of an insulating substance bonded onto the surface of the non-porous monocrystalline semiconductor region; PA1 to provide a semiconductor member comprising: PA1 a first member having a non-porous monocrystalline semiconductor region and a region constituted of an insulating substance arranged in this order on a porous monocrystalline semiconductor region, and PA1 a second member bonded through a region constituted of an insulating substance onto the surface of the region constituted of the insulating substance; PA1 to provide a semiconductor member having a non-porous silicon monocrystalline semiconductor region arranged on a region constituted of an insulating substance, characterized in that the dislocation defect density in the non-porous silicon monocrystalline semiconductor region is 2.0.times.10.sup.4 /cm.sup.2 or less, and the life time of carriers is 5.0.times.10.sup.-4 second or longer; and PA1 to provide a semiconductor member having a non-porous silicon monocrystalline semiconductor region arranged on a region constituted of an insulating substance, characterized in that the dislocation defect density in the non-porous silicon monocrystalline semiconductor region is 2.0.times.10.sup.4 /cm.sup.2 or less, and the life time of carriers is 5.0.times.10.sup.-4 sec or longer, and also the difference between the maximum value and the minimum value of the thickness of the silicon monocrystalline semiconductor region is 10% or less with respect to maximum value.
In order to realize the many advantages in device characteristics as mentioned above, studies have been made about the method for forming the SOI structure for these some 10 years. The contents are summarized in, for example, the literature as mentioned below:
Special Issue: "Single-crystal silicon on non-single-crystal insulators"; edited by G. W. Cullen, Journal of Crystal Growth, volume 63, No.3, pp. 429-533 (1983).
Also, it has been known for a long time to for the SOS (silicon on sapphire) structure by heteroepitaxy of Si on a monocrystalline sapphire substrate by CVD (chemical vapor deposition) method. This was successful to some extent as the most mature SOI technique, but for such reasons as a large amount of crystal defects because of lattice mismatching at the interface between the Si layer and the sapphire substrate, introduction of aluminum from the sapphire substrate into the Si layer, and above all the high cost of the substrate and delay in enlargement of the substrate wafer size, it is obstructed from being widely applied. Relatively in recent years, attempts to realize the SOI structure without use of a sapphire substrate have been done. Such attempts may be broadly classified into the three shown below.
As the means for realizing the above (1), there have been known the method in which a monocrystalline Si layer is formed directly to lateral epitaxial growth by CVD, the method in which amorphous Si is deposited and subjected to solid phase lateral epitaxial growth by heat treatment, the method in which amorphous or polycrystalline Si layer is irradiated convergently with an energy beam such as electron beam, laser beam, etc. and a monocrystalline layer is grown on SiO.sub.2 by melting and recrystallization, and the method in which a melting region is scanned in a zone fashion by a rod-shaped heater (Zone melting recrystallization). These methods have both advantages and disadvantages. They still have many problems with respect to controllability, productivity, uniformity and quality, and none of them have been industrially applied yet to date. For example, the CVD method requires sacrifice-oxidation in flat thin film formation, while the crystallinity is poor in the solid phase growth method. On the other hand, in the beam annealing method, problems are involved in controllability such as treatment time by converged beam scanning, the manner of overlapping of beams, focus adjustment, etc. Among these, the Zone Melting Recrystallization method is the most mature, and a relatively larger scale integrated circuit has been trially made, but still a large number of crystal defects such as point defect, line defect, plane defect (sub-boundary), etc. remain, and no device driven by minority carriers has been prepared.
Concerning the method using no Si substrate as the seed for epitaxial growth which is the above method (2), for example, the following methods may be included.
As the method (3) as described above, the method described in Japanese Laid-open Patent Application No. 55-16464 has the steps of forming an N-type monocrystalline Si layer on a P-type Si wafer, providing a glass layer containing an oxide of the N-type impurity thereon and the step of bonding the glass layer to a glass layer containing the oxide of an N-purity impurity provided on another silicon wafer by heat treatment. And, subsequent to the bonding step, the P-type Si wafer is made porous, and then the porous layer is oxidized, followed by etching to remove the porous layer, thereby forming an SOI structure. Also, Japanese Patent Publication No. 53-45675 discloses a method in which a silicon monocrystalline wafer is made porous, then oxidized to make the porous layer higher in resistance; a monocrystalline Si layer is formed on the porous silicon layer; and a part of the monocrystalline Si layer is made porous and higher in resistance so as to surround the monocrystalline Si region, thereby separating the monocrystalline Si region.
The methods described in these publications all include the step of oxidizing a porous layer, and because the volume of porous layer is increased by oxidation, sometimes an influence of distortion may be exerted on the monocrystalline Si layer, and therefore in these methods, a monocrystalline Si layer with constantly good quality could not necessarily be formed on the insulator.